# SPDX-License-Identifier: MIT
# Copyright 2023-2024 RnD Center "ELVEES", JSC

# MDB script to start sbl-s1, ddrinit, TF-A and U-Boot on MCom-03 SoC. Script uses DDR0.

pb python
pb import os
pb import sys
pb IMAGES_PATH = os.environ.get('MDB_IMAGES_PATH', 'buildroot/output/images')
pb SCRIPTS_PATH = f'{IMAGES_PATH}/sbl/scripts'
pb sys.path.append(SCRIPTS_PATH)
pb import helpers
pb end

pb python
pb dtb = os.environ.get('MDB_DTB_FILE', 'mcom03-mcom03bub-r1.3.0.dtb')
pb map_file = os.environ.get('MDB_DDRINIT_DTB_MAP', 'mcom03-ddrinit-dtb-map.txt')
pb board = helpers.parse_ddrinit_dtb_map(f'{SCRIPTS_PATH}/{map_file}', dtb)
pb end

# Load and run sbl-s1 to setup required clocks
py helpers.loadelf(f'{IMAGES_PATH}/sbl/sbl-s1.elf')
hbp set jtag
run
hbp unset jtag

# Initialize and configure the TOP clock gate for MEDIA, CPU, SDR channels
pb python
pb top = helpers.get_32bit(0xbf001008)
pb top_clk_gate_media = 1
pb top_clk_gate_cpu = 2
pb top_clk_gate_sdr = 3
pb top |= (1 << top_clk_gate_media) | (1 << top_clk_gate_cpu) | (1 << top_clk_gate_sdr)
pb helpers.set_32bit(0xbf001008, top)
pb end

# Load and run ddrinit to setup DDR memory
py helpers.loadelf(f'{IMAGES_PATH}/ddrinit-{board}/ddrinit.elf')
hbp set jtag
run
hbp unset jtag

# Load and run set-secure-regions.elf to setup Secure Regions and
# to take them into account in the DDR memory map
py helpers.loadelf(f'{IMAGES_PATH}/sbl/scripts/set-secure-regions.elf')
hbp set jtag
run
hbp unset jtag

# Load U-Boots dtb to 0x8_9040_2000 which is mapped to 0xC0002000
py helpers.loadbin(f'{IMAGES_PATH}/uboot-dtb/{dtb}', 0xC0002000)

# Load TF-A to 0x8_8030_0000 which is mapped to 0xc0300000
py helpers.loadbin(f'{IMAGES_PATH}/bl31.bin', 0xc0300000)

# Load U-Boot to 0x8_9048_0000 which is mapped to 0xc0080000
py helpers.loadbin(f'{IMAGES_PATH}/u-boot.bin', 0xc0080000)

# Enable CPU_SUBS
set 0xbf000000 0x10

# Enable core clk and dbus clk (sys clk is enabled by default)
set 0xa1080004 0x2
set 0xa1080008 0x2

# All CPU clocks to bypass mode
set 0xa1080040 0x7

# Setup CPU PLL to 1161 MHz, assuming that XTI = 27 MHz
# Should be the same as set in SBL
set 0xa1000050 0x154601

# Set CPU clock dividers
set 0xa1080000 0x1002
set 0xa1080004 0x402
set 0xa1080008 0x802

# Set CPU_UCG_SYNC
set 0xa1080044 0x7

# Disable bypass mode for CPU clocks
set 0xa1080040 0x0

# Enable a53sys_ppolicy
set 0xa1000040 0x10

# Setup reset address for CPU0 cores
set 0xa1000118 0x8
set 0xa100011C 0x80300000
set 0xa1000120 0x8
set 0xa1000124 0x80300000
set 0xa1000128 0x8
set 0xa100012C 0x80300000
set 0xa1000130 0x8
set 0xa1000134 0x80300000

# Enable CPU0 core0
set 0xa1000000 0x10

quit