Index of /mcom02/baremetal/projects/MCS4_samples/ddr_init/MultiCore_Configuration_Debug

	Name	Last modified	Size
	Parent Directory		-
	ddr/	2021-04-27 11:07	-
	mcom_runtime/	2021-04-27 11:07	-
	DSP1.xl	2021-03-12 09:19	347
	DSP2.xl	2021-03-12 09:19	347
	DSP3.xl	2021-03-12 09:19	347
	Project.xl	2021-03-12 09:19	2.9K
	__DSP0__.o	2021-03-12 09:19	264
	__DSP0__.o0	2021-03-12 09:19	409
	__DSP1__.o	2021-03-12 09:19	264
	__DSP1__.o1	2021-03-12 09:19	409
	__DSP2__.o	2021-03-12 09:19	264
	__DSP2__.o2	2021-03-12 09:19	409
	__DSP3__.o	2021-03-12 09:19	264
	__DSP3__.o3	2021-03-12 09:19	409
	__DSPX__.xx	2021-03-12 09:19	445
	ddr_init.elf	2021-03-12 09:19	79K
	main.o	2021-03-12 09:19	3.0K
	makefile	2021-03-12 09:19	4.0K
	objects.mk	2021-03-12 09:19	253
	output.map	2021-03-12 09:19	57K
	sources.mk	2021-03-12 09:19	822
	subdir.mk	2021-03-12 09:19	939