#ifndef _PDMA_H_ #define _PDMA_H_ #define PDMA_MAX_BLOCK_SIZE 4095 #define PDMA_BASE 0x38000000 #define PDMA_CHAN0 0x0000 #define PDMA_CHAN1 0x0058 #define PDMA_CHAN2 0x00B0 #define PDMA_CHAN3 0x0108 #define PDMA_CHAN4 0x0160 #define PDMA_CHAN5 0x01B8 #define PDMA_CHAN6 0x0210 #define PDMA_CHAN7 0x0268 #define PDMA_SAR0 0x0000 #define PDMA_DAR0 (PDMA_SAR0+8) ///0x0008 #define PDMA_LLP0 (PDMA_SAR0+16) ///0x0010 #define PDMA_CTL0 (PDMA_SAR0+24) ///0x0018 #define PDMA_SSTAT0 (PDMA_SAR0+32) ///0x0020 #define PDMA_DSTAT0 (PDMA_SAR0+40) ///0x0028 #define PDMA_SSTATAR0 (PDMA_SAR0+48) ///0x0030 #define PDMA_DSTATAR0 (PDMA_SAR0+56) ///0x0038 #define PDMA_CFG0 (PDMA_SAR0+64) ///0x0040 #define PDMA_SGR0 (PDMA_SAR0+72) ///0x0048 #define PDMA_DSR0 (PDMA_SAR0+80) ///0x0050 #define PDMA_CHN PDMA_CHAN1 #define PDMA_SAR1 (PDMA_CHN) #define PDMA_DAR1 (PDMA_CHN+8) #define PDMA_LLP1 (PDMA_CHN+16) #define PDMA_CTL1 (PDMA_CHN+24) #define PDMA_SSTAT1 (PDMA_CHN+32) #define PDMA_DSTAT1 (PDMA_CHN+40) #define PDMA_SSTATAR1 (PDMA_CHN+48) #define PDMA_DSTATAR1 (PDMA_CHN+56) #define PDMA_CFG1 (PDMA_CHN+64) #define PDMA_SGR1 (PDMA_CHN+72) #define PDMA_DSR1 (PDMA_CHN+80) #undef PDMA_CHN #define PDMA_CHN PDMA_CHAN2 #define PDMA_SAR2 (PDMA_CHN) #define PDMA_DAR2 (PDMA_CHN+8) #define PDMA_LLP2 (PDMA_CHN+16) #define PDMA_CTL2 (PDMA_CHN+24) #define PDMA_SSTAT2 (PDMA_CHN+32) #define PDMA_DSTAT2 (PDMA_CHN+40) #define PDMA_SSTATAR2 (PDMA_CHN+48) #define PDMA_DSTATAR2 (PDMA_CHN+56) #define PDMA_CFG2 (PDMA_CHN+64) #define PDMA_SGR2 (PDMA_CHN+72) #define PDMA_DSR2 (PDMA_CHN+80) #undef PDMA_CHN #define PDMA_CHN PDMA_CHAN3 #define PDMA_SAR3 (PDMA_CHN) #define PDMA_DAR3 (PDMA_CHN+8) #define PDMA_LLP3 (PDMA_CHN+16) #define PDMA_CTL3 (PDMA_CHN+24) #define PDMA_SSTAT3 (PDMA_CHN+32) #define PDMA_DSTAT3 (PDMA_CHN+40) #define PDMA_SSTATAR3 (PDMA_CHN+48) #define PDMA_DSTATAR3 (PDMA_CHN+56) #define PDMA_CFG3 (PDMA_CHN+64) #define PDMA_SGR3 (PDMA_CHN+72) #define PDMA_DSR3 (PDMA_CHN+80) #undef PDMA_CHN #define PDMA_CHN PDMA_CHAN4 #define PDMA_SAR4 (PDMA_CHN) #define PDMA_DAR4 (PDMA_CHN+8) #define PDMA_LLP4 (PDMA_CHN+16) #define PDMA_CTL4 (PDMA_CHN+24) #define PDMA_SSTAT4 (PDMA_CHN+32) #define PDMA_DSTAT4 (PDMA_CHN+40) #define PDMA_SSTATAR4 (PDMA_CHN+48) #define PDMA_DSTATAR4 (PDMA_CHN+56) #define PDMA_CFG4 (PDMA_CHN+64) #define PDMA_SGR4 (PDMA_CHN+72) #define PDMA_DSR4 (PDMA_CHN+80) #undef PDMA_CHN #define PDMA_CHN PDMA_CHAN5 #define PDMA_SAR5 (PDMA_CHN) #define PDMA_DAR5 (PDMA_CHN+8) #define PDMA_LLP5 (PDMA_CHN+16) #define PDMA_CTL5 (PDMA_CHN+24) #define PDMA_SSTAT5 (PDMA_CHN+32) #define PDMA_DSTAT5 (PDMA_CHN+40) #define PDMA_SSTATAR5 (PDMA_CHN+48) #define PDMA_DSTATAR5 (PDMA_CHN+56) #define PDMA_CFG5 (PDMA_CHN+64) #define PDMA_SGR5 (PDMA_CHN+72) #define PDMA_DSR5 (PDMA_CHN+80) #undef PDMA_CHN #define PDMA_CHN PDMA_CHAN6 #define PDMA_SAR6 (PDMA_CHN) #define PDMA_DAR6 (PDMA_CHN+8) #define PDMA_LLP6 (PDMA_CHN+16) #define PDMA_CTL6 (PDMA_CHN+24) #define PDMA_SSTAT6 (PDMA_CHN+32) #define PDMA_DSTAT6 (PDMA_CHN+40) #define PDMA_SSTATAR6 (PDMA_CHN+48) #define PDMA_DSTATAR6 (PDMA_CHN+56) #define PDMA_CFG6 (PDMA_CHN+64) #define PDMA_SGR6 (PDMA_CHN+72) #define PDMA_DSR6 (PDMA_CHN+80) #undef PDMA_CHN #define PDMA_CHN PDMA_CHAN7 #define PDMA_SAR7 (PDMA_CHN) #define PDMA_DAR7 (PDMA_CHN+8) #define PDMA_LLP7 (PDMA_CHN+16) #define PDMA_CTL7 (PDMA_CHN+24) #define PDMA_SSTAT7 (PDMA_CHN+32) #define PDMA_DSTAT7 (PDMA_CHN+40) #define PDMA_SSTATAR7 (PDMA_CHN+48) #define PDMA_DSTATAR7 (PDMA_CHN+56) #define PDMA_CFG7 (PDMA_CHN+64) #define PDMA_SGR7 (PDMA_CHN+72) #define PDMA_DSR7 (PDMA_CHN+80) #undef PDMA_CHN typedef volatile struct { volatile unsigned long long SAR; volatile unsigned long long DAR; volatile unsigned long long LLP; volatile unsigned long long CTL; volatile unsigned long long SSTAT; volatile unsigned long long DSTAT; volatile unsigned long long SSTATAR; volatile unsigned long long DSTATAR; volatile unsigned long long CFG; volatile unsigned long long SGR; volatile unsigned long long DSR; } pdma_mem_channel; typedef struct { unsigned int SAR; unsigned int DAR; unsigned int LLP; unsigned long long int CTL; unsigned int SSTAT; unsigned int DSTAT; } pdma_mem_chain; #define _MemCh ((pdma_mem_channel volatile *)PDMA_BASE) #define DmaCfgReg *((volatile unsigned long long *)(PDMA_BASE + 0x398)) #define ChEnReg *((volatile unsigned long long *)(PDMA_BASE + 0x3a0)) #define DmaIdReg *((volatile unsigned long long *)(PDMA_BASE + 0x3a8)) #define DmaTestReg *((volatile unsigned long long *)(PDMA_BASE + 0x3b0)) pdma_mem_channel* get_pdma_dev(int dma_id); int pdma_configure(int dma_id, void * dst, const void * src, int size); int pdma_run(int dma_id); int pdma_wait(int dma_id); int pdma_copy(unsigned int dma_id, void * dst, const void * src, unsigned int size); pdma_mem_chain * pdma_fill_link(pdma_mem_chain *link, void * dst, void * src, unsigned int size, unsigned int llp_en); int pdma_start_chain(int ch, pdma_mem_chain *link); #endif