smc_rd_wr_type

smc_bit_depth

enum smc_status SMC_SetOpmode(SMC_Type *base, enum smc_burst_align align, enum smc_bls bls, enum smc_adv adv, enum smc_packet_lenght wr_lenght, enum smc_rd_wr_type wr_sync, enum smc_packet_lenght rd_lenght, enum smc_rd_wr_type rd_sync, enum smc_bit_depth depth)

smc_packet_lenght

smc_burst_align

enum smc_status SMC_DirectCmd(SMC_Type *base, uint32_t chip_select, enum smc_cmd_type cmd_type, enum smc_cre set_cre, uint32_t addr)

smc_status

enum smc_status SMC_UserConfig(SMC_Type *base, enum smc_incr_to_incr4 bank0, enum smc_incr_to_incr4 bank1, uint32_t smcclkdiv)

enum smc_status SMC_PowerSaveOff(SMC_Type *base)

smc_cre

smc_cmd_type

enum smc_status SMC_SetCycles(SMC_Type *base, uint32_t ttr, uint32_t tpc, uint32_t twp, uint32_t tceoe, uint32_t twc, uint32_t trc)

smc_incr_to_incr4

smc_bls

enum smc_status SMC_PowerSaveOn(SMC_Type *base)

enum smc_status SMC_RefreshPeriod(SMC_Type *base, uint32_t period)

bool SMC_CheckConfigure(SMC_Type *base, uint32_t chip_select, uint32_t cycles, uint32_t mode)

smc_adv

@ SMC_RdWrAsync

@ SMC_RdWrSync

@ SMC_BitDepth8

@ SMC_BitDepth32

@ SMC_BitDepth24

@ SMC_BitDepth16

@ SMC_PacketLenght4

@ SMC_PacketLenght1

@ SMC_PacketLenghtEndless

@ SMC_PacketLenght8

@ SMC_BurstAlign128

@ SMC_BurstAlignNo

@ SMC_BurstAlign64

@ SMC_BurstAlign256

@ SMC_BurstAlign32

@ SMC_Status_InvalidArgument

@ SMC_Status_Ok

@ SMC_CRE0

@ SMC_CRE1

@ SMC_CmdTypeModeReg

@ SMC_CmdTypeUpdateRegsAndAHBCommand

@ SMC_CmdTypeUpdateRegs

@ SMC_CmdTypeModeRegAndUpdateRegs

@ SMC_IncrToIncr4Disable

@ SMC_IncrToIncr4Enable

@ SMC_BlsAsNcs

@ SMC_BlsAsNwe

@ SMC_AdvMemory

@ SMC_AdvUsed

@ SMC_AdvNotUsed

@ SMC_AdvLcd